Synchronous dynamic random-access memory (SDRAM) is one class of memory used in mobile communication and computing devices, such as smart phones and tablet computers. In some embodiments, double data rate SDRAM (DDR SDRAM or DDR) refers to a type of memory and an associated interface for communicating with the memory. Furthermore, low power DDR (LPDDR or simply LP), sometimes referred to as mobile DDR, is a class of DDR designed to reduce power consumption, with mobile devices being a target application. There are several versions of LPDDR corresponding to various data speeds and power requirements. For example, LPDDR3 (also sometimes denoted as LP3) and LPDDR4 (also sometimes denoted as LP4) are two recent versions of LPDDR. LPDDR4 is designed to communicate at a higher speed and consume less power than LPDDR3 at the expense of increased cost and/or complexity.
A trend in modern mobile devices, such as smartphones, is to focus memory designs on ever greater memory transfer rate while at the same time conserving power. A system on chip (SoC) is often used in mobile devices to conserve power and/or minimize space requirements. A SoC refers to multiple functional blocks, such as modems and application processor cores, embedded on a single substrate, allowing mobile devices to execute complex and power intensive applications. The single substrate is sometimes referred to as a die, so multiple functional blocks are commonly implemented on a single die.
The current generation of low power double data rate (LPDDR4) DRAM uses n-type Field Effect Transistors (NFETs) for both the pull-up and pull-down driver in its interface. In addition, an on-die termination (ODT) device (such as a transistor) may be switched on when receiving data to present a desired impedance to a receive line. This is commonly referred to as the terminated mode. The pull-up and pull-down transistors are tuned to also present the desired impedance (e.g., 50 Ohms) when they are switched on during data transmission.
The power supply voltage (VDDQ) for a conventional LPDDR4 interface is typically around 1.1V. In a terminated high-speed mode of operation in which the ODT transistor is active in the receiving node, the pull-up transistor in the transmitting device and the ODT transistor in the receiving device effectively form a voltage divider that divides the source voltage for the pull-up transistor by one-half. The source voltage for the pull-up transistor when active is VDDQ minus its threshold voltage such that the source voltage varies between a minimum of 550 mV to a maximum of 888 mV (the average being around 720 mV). Due to the voltage divider formed as just discussed, the receiving device will thus receive a voltage of approximately 350 mV on average when the pull-up device is active. When the pull-down device is active, the received voltage is ground such that the voltage swing at the receiving node for the terminated high-speed mode is approximately 350 mV.
But the active ODT device in the terminated mode consumes DC power. Thus, if the current data transmission does not require the bandwidth of the terminated high-speed mode, an unterminated reduced speed mode may be used. In the unterminated mode, the ODT device is switched off. Since the receiving device has its ODT device turned off in the unterminated mode, there is very little or no consumption of DC power. But the voltage swing is then equal to the source voltage of the pull-up device (550 mv to 888 mv as just described). The AC power is proportional to the square of the voltage swing such that the AC power consumption in the unterminated mode is approximately four times what the AC power consumption is in the terminated mode.
There is thus a need in the art for improved unterminated modes for memory interfaces.